3.5.6. AXI#

3.5.6.1. AXI Subordinate#

namespace simbricks#

Functions

inline uint64_t pow2(uint64_t exponent)#
struct AXIOperation#

Public Functions

inline AXIOperation(uint64_t addr, size_t len, uint64_t axi_id, size_t step_size)#

Public Members

uint64_t addr#
size_t len#
uint64_t id#
std::unique_ptr<uint8_t[]> buf#
size_t step_size#
bool completed = false#
template<size_t BytesAddr, size_t BytesId, size_t BytesData, size_t MaxInFlight = 16>
class AXISubordinateRead#

Public Functions

inline AXISubordinateRead(const uint8_t *const ar_addr, const uint8_t *const ar_id, uint8_t &ar_ready, const uint8_t &ar_valid, const uint8_t &ar_len, const uint8_t &ar_size, const uint8_t &ar_burst, uint8_t *const r_data, uint8_t *const r_id, const uint8_t &r_ready, uint8_t &r_valid, uint8_t &r_last)#
void read_done(uint64_t axi_id, const uint8_t *data)#
void step(uint64_t cur_ts)#
void step_apply()#

Protected Functions

virtual void do_read(const AXIOperation &axi_op) = 0#

Private Functions

void send_next_data_segment()#

Private Members

const uint8_t *const ar_addr_#
const uint8_t *const ar_id_#
uint8_t &ar_ready_#
const uint8_t &ar_valid_#
const uint8_t &ar_len_#
const uint8_t &ar_size_#
const uint8_t &ar_burst_#
uint8_t *const r_data_#
uint8_t *const r_id_#
const uint8_t &r_ready_#
uint8_t &r_valid_#
uint8_t &r_last_#
uint8_t ar_ready_tmp_ = 0#
uint8_t r_valid_tmp_ = 0#
uint8_t r_last_tmp_ = 0#
uint8_t r_data_tmp_[BytesData] = {0}#
uint32_t r_id_tmp_#
uint64_t main_time_ = 0#
std::deque<AXIOperation> pending_ = {}#
std::unordered_map<uint64_t, std::reference_wrapper<AXIOperation>> id_op_map_ = {}#
AXIOperation *cur_op_ = nullptr#
size_t cur_off_ = 0#
uint32_t rolling_id_ = 0#
template<size_t BytesAddr, size_t BytesId, size_t BytesData, size_t MaxInFlight = 16>
class AXISubordinateWrite#

Public Functions

inline AXISubordinateWrite(const uint8_t *aw_addr, const uint8_t *aw_id, uint8_t &aw_ready, const uint8_t &aw_valid, const uint8_t &aw_len, const uint8_t &aw_size, const uint8_t &aw_burst, const uint8_t *w_data, uint8_t &w_ready, const uint8_t &w_valid, const uint8_t &w_strb, const uint8_t &w_last, uint8_t *b_id, const uint8_t &b_ready, uint8_t &b_valid, uint8_t &b_resp)#
void write_done(uint64_t axi_id)#
void step(uint64_t cur_ts)#
void step_apply()#

Protected Functions

virtual void do_write(const AXIOperation &axi_op) = 0#

Private Members

const uint8_t *const aw_addr_#
const uint8_t *const aw_id_#
uint8_t &aw_ready_#
const uint8_t &aw_valid_#
const uint8_t &aw_len_#
const uint8_t &aw_size_#
const uint8_t &aw_burst_#
const uint8_t *const w_data_#
uint8_t &w_ready_#
const uint8_t &w_valid_#
const uint8_t &w_strb_#
const uint8_t &w_last_#
uint8_t *const b_id_#
const uint8_t &b_ready_#
uint8_t &b_valid_#
uint8_t &b_resp_#
uint8_t aw_ready_tmp_ = 0#
uint8_t w_ready_tmp_ = 0#
uint8_t b_valid_tmp_ = 0#
uint64_t b_id_tmp_ = 0#
uint64_t main_time_ = 0#
uint64_t cur_off_ = 0#
uint64_t num_pending_ = 0#
std::optional<AXIOperation> cur_op_ = std::nullopt#

3.5.6.2. AXIL Manager#

namespace simbricks
struct AXILOperationR#

Public Functions

inline AXILOperationR(uint64_t addr, uint64_t req_id)#

Public Members

uint64_t addr#
uint64_t req_id#
uint64_t data = 0#
struct AXILOperationW#

Public Functions

inline AXILOperationW(uint64_t addr, uint64_t req_id, uint64_t data, bool posted)#

Public Members

uint64_t addr#
uint64_t req_id#
uint64_t data#
bool posted#
template<size_t BytesAddr, size_t BytesData>
class AXILManagerReadPort#

Public Functions

inline AXILManagerReadPort(uint8_t *ar_addr, const uint8_t &ar_ready, uint8_t &ar_valid, const uint8_t *r_data, uint8_t &r_ready, const uint8_t &r_valid, uint8_t &r_resp, std::function<void()> op_done_cb)#
void step(uint64_t cur_ts)#
void step_apply()#
inline void set_op(AXILOperationR &axi_op)#

Private Members

uint8_t *const ar_addr_#
const uint8_t &ar_ready_#
uint8_t &ar_valid_#
const uint8_t *const r_data_#
uint8_t &r_ready_#
const uint8_t &r_valid_#
uint8_t &r_resp_#
uint8_t ar_valid_tmp_ = 0#
uint64_t ar_addr_tmp_ = 0#
uint64_t main_time_ = 0#
AXILOperationR *cur_op_ = nullptr#
std::function<void()> op_done_cb_#
bool handling_op_ = false#
template<size_t BytesAddr, size_t BytesData>
class AXILManagerWritePort#

Public Functions

inline AXILManagerWritePort(uint8_t *aw_addr, const uint8_t &aw_ready, uint8_t &aw_valid, uint8_t *w_data, const uint8_t &w_ready, uint8_t &w_valid, uint8_t &w_strb, uint8_t &b_ready, const uint8_t &b_valid, const uint8_t &b_resp, std::function<void()> op_done_cb)#
void step(uint64_t cur_ts)#
void step_apply()#
inline void set_op(AXILOperationW &axi_op)#

Private Members

uint8_t *const aw_addr_#
const uint8_t &aw_ready_#
uint8_t &aw_valid_#
uint8_t *const w_data_#
const uint8_t &w_ready_#
uint8_t &w_valid_#
uint8_t &w_strb_#
uint8_t &b_ready_#
const uint8_t &b_valid_#
const uint8_t &b_resp_#
uint8_t aw_valid_tmp_ = 0#
uint64_t aw_addr_tmp_ = 0#
uint8_t w_valid_tmp_ = 0#
uint64_t w_data_tmp_ = 0#
uint64_t main_time_ = 0#
AXILOperationW *cur_op_ = nullptr#
std::function<void()> op_done_cb_#
bool handling_op_ = false#
template<size_t BytesAddr, size_t BytesData>
class AXILManager#

Public Functions

inline AXILManager(uint8_t *ar_addr, const uint8_t &ar_ready, uint8_t &ar_valid, const uint8_t *r_data, uint8_t &r_ready, const uint8_t &r_valid, uint8_t &r_resp, uint8_t *aw_addr, const uint8_t &aw_ready, uint8_t &aw_valid, uint8_t *w_data, const uint8_t &w_ready, uint8_t &w_valid, uint8_t &w_strb, uint8_t &b_ready, const uint8_t &b_valid, const uint8_t &b_resp)#
void step(uint64_t cur_ts)#
void step_apply()#
void issue_read(uint64_t req_id, uint64_t addr)#
void issue_write(uint64_t req_id, uint64_t addr, uint64_t data, bool posted)#

Protected Functions

virtual void read_done(AXILOperationR &axi_op) = 0#
virtual void write_done(AXILOperationW &axi_op) = 0#

Private Types

enum [anonymous]#

Values:

enumerator NONE#
enumerator READ#
enumerator WRITE#
using ReadPortT = AXILManagerReadPort<BytesAddr, BytesData>#
using WritePortT = AXILManagerWritePort<BytesAddr, BytesData>#

Private Functions

void op_done()#
void ports_set_op()#

Private Members

ReadPortT read_port_#
WritePortT write_port_#
std::deque<std::variant<AXILOperationR, AXILOperationW>> pending_ = {}#
enum simbricks::AXILManager::[anonymous] step_on_ = NONE#